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Espressif Systems /ESP32-P4 /I3C_SLV /DATACTRL

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Interpret as DATACTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FLUSHTB)FLUSHTB 0 (FLUSHFB)FLUSHFB 0 (UNLOCK)UNLOCK 0TXTRIG 0RXTRIG 0TXCOUNT0RXCOUNT0 (TXFULL)TXFULL 0 (RXEMPTY)RXEMPTY

Description

NA

Fields

FLUSHTB

Flushes the from-bus buffer/FIFO. Not normally used
FLUSHFB

Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message prematurely
UNLOCK

If this bit is not written 1, the register bits from 7 to 4 are not changed on write.
TXTRIG

Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3
RXTRIG

Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3
TXCOUNT

NA
RXCOUNT

NA
TXFULL

NA
RXEMPTY

NA

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd